1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device manufactured by the method, and more particularly to a technique of flattening a film on a semiconductor substrate having a trench-type device isolation structure.
2. Description of the Background Art
In order to control devices in a completely independent manner during operation in a semiconductor integrated circuit, it is necessary to eliminate electric interference between the devices. For this reason, a device isolation structure having a device isolation region is adopted in the semiconductor integrated circuit, and a trench isolation method is widely known as a method of manufacturing the device isolation structure and a number of improvements in this field have been suggested.
In the trench isolation method, a trench is so formed as to extend inwardly from a surface of the substrate and the trench is filled with a dielectric. Since this device isolation method causes little bird's beak which would be found in a device isolation structure made by LOCOS and needs a smaller area on the surface of the substrate for forming the device isolation structure than the LOCOS, this method, being favorable for size reduction of the semiconductor integrated circuit, is indispensable in a field of semiconductor integrated circuit whose size should be more reduced in future.
In order to achieve the device isolation by the trench isolation method, it is required to bury the dielectric without creating any seam (keyhole-shaped cross-sectional void) inside a trench having a small opening. Among good methods to meet this requirement is a film-formation method such as HDP-CVD (High Density Plasma - Chemical Vapor Deposition) in which an etching and a deposition are simultaneously performed. The following discussion will be made taking the HDP-CVD as an example.
As compared with conventional methods such as a low pressure CVD, the method using the HDP-CVD for burying the dielectric in the trench has the following characteristic features: (a) a film to be formed in the device isolation region can be buried almost flatly to have the same film thickness, not depending on an isolation width, i.e., an opening width of the trench; on the other hand, (b) a section of a film to be deposited on an active region where devices are to be formed depends on a width of the active region and a protrusion having a triangle or trapezoidal section is formed in the active region. Sloped planes of the protrusion are formed at an angle of tilt of 45 degrees with respect to the surface of the substrate from an end portion of the active region. Therefore, the protrusion is of trapezoidal if the active region has a width twice as large as or more than the thickness of the film to be formed.
In a process of manufacturing a size-reduced and multilayered integrated circuit including the step of the forming the above-mentioned device isolation structure, with reduction of focus margin in a photolithography process and reduction in the amount of film to be overetched in an etching process, it is important to ensure flatness of layers formed on the substrate. Therefore, the CMP is widely adopted when the above-mentioned protrusion is removed and an uppermost surface of the substrate after forming the trench isolation structure is flattened.
Now, with reference to cross sections of FIGS. 22 to 26, the prior-art method of manufacturing a semiconductor device as mentioned above will be discussed.
First, a silicon oxide film 102 and a silicon nitride film 103 are formed on one surface of a semiconductor substrate 101 in this order.
With a photolithography pattern as a mask, a trench 121 is so formed as to extend from a surface of the silicon nitride film 103 inwardly to a predetermined depth the substrate 101 by dry etching as shown in FIG. 22.
Subsequently, a silicon oxide film 111 is deposited by HDP-CVD in the trench 121 serving as a device isolation region 120 and on an active region 130 which is a region other than the trench 121, to be buried in the trench 121 as shown in FIG. 23. As shown in FIG. 22, some regions of the device isolation region 120 and some regions of the active region 130 should be individually distinguished, each of these regions are represented by a reference sign of reference numeral and alphabet, specifically as the device isolation regions 120A, 120C and 120E and the active regions 130B, 130D and 130F. Elements in the device isolation region 120 and the active region 130 are also represented by reference signs of reference numerals and corresponding alphabets to make a distinction of belonging. The same applies to FIG. 23 and the following figures.
Next, the silicon oxide film 111 on the silicon nitride film 103 is removed by CMP with the silicon nitride film 103 as a stopper film (hardmask laser) for polishing, and thereafter a buried oxide 111 made of the silicon oxide film 111 is formed in the trench 121 as shown in FIG. 24.
The silicon nitride film 103 is removed with thermal phosphoric acid as shown in FIG. 25, and subsequently the silicon oxide film 102 is removed with hydrofluoric acid to obtain a trench-type device isolation structure shown in FIG. 26.
The prior-art method of forming the trench-type device isolation structure has the following problems. (Problem 1) Since the CMP is a method to equally polish the whole surface to be polished, when a surface layer with great unevenness such as the silicon oxide film 111 of FIG. 23 is polished by CMP, if the amount of oxide film to be polished is determined in accordance with the thickest portion of the silicon oxide film 111 on the silicon nitride film 103, e.g., the silicon oxide film 111F of FIG. 23, the silicon nitride film 103 which originally serves as a stopper film is also unnecessarily polished as shown in FIG. 24 in the thinnest portion of the silicon oxide 111 on the silicon nitride film 103, e.g., the silicon oxide film 111B of FIG. 23. Therefore, in the flattening method using CMP, a shape of the polished buried oxide 111 depends on the above-mentioned pattern as shown in FIG. 24 and a height of the buried oxide 111 (a length from a bottom of the trench 121 to the uppermost surface of the buried oxide 111) is disadvantageously not uniform in the surface of the substrate 111 as shown in FIG. 26.
Anyway, as mentioned earlier, the film-formation method such as HDP-CVD in which the etching and the deposition are simultaneously performed is indispensable in the field of manufacture of a semiconductor device whose size should be more reduced in future since the method allows the silicon oxide film 111 to be buried almost flatly with uniform thickness without creating any seam inside a trench even if the trench has a small opening. Therefore, it is desired that the buried oxide film 111 formed by HDP-CVD should be flattened without the above-mentioned problem.
As a solution to the above-mentioned problem, U.S. Pat. No. 5,498,565 discloses a method using etching and CMP together for flattening a silicon oxide film formed by HDP-CVD. In this flattening method, an unevenness to be polished is flattened by photolithography and etching to so that the surface can be polished by CMP before polishing by CMP. This prior-art method including two steps of etching and CMP, however, has a problem that the flattening process becomes more complicate than the conventional flattening method using only CMP.
(Problem 2) The conventional method of forming a trench-type device isolation has a disadvantage that the unit price of device increases since it uses CMP which costs high.
It is desired to provide a method not using CMP for flattening a buried oxide film formed by HDP-CVD, to solve Problems 1 and 2.